Course Weekly Lecture Plan

Week	Topic
1	Introduction, CPU, Evolution
2	Pipeline
3	Instruction pipeline, Pipeline hazards, solutions
4	I/O Organization Handshaking, CPU-memory interaction
5	I/O Operations Asynchronous bus access
6	Midterm (It will be arranged according to current academic calendar. It may change due to holidays.) Follow the announcements.
7	Interrupts, Serial/ parallel interrupt priority circuits
8	Direct Memory Access -DMA
9	Direct Memory Access -DMA
10	Cache Memory
11	Midterm (It will be arranged according to current academic calendar. It may change due to holidays.) Follow the announcements.
12	Cache Memory
13	RAID: (Redundant Array of Independent/Inexpensive Disks) Error detection / correction
14	Multiple Processor organizations Cache coherence and MESI protocol