Course Information

Course Name	Turkish	Sayısal Devreler
	English	Digital Circuits
Course Code	BLG 231	Credit	Lecture (hour/week)	Recitation (hour/week)	Laboratory (hour/week)
Semester	4	3	3	-	-
Course Language		Turkish
Course Coordinator		Taşdemir Aşan
Course Objectives		Initial course in Boole algebra, combinational logic design, synchronous sequential circuit analysis and synthesis.
Course Description		Characteristics of digital systems; Number systems, arithmetical operations with binary numbers; Fundamentals of Boolean Algebra; Logic functions, canonical and standard forms; Logic gates. Implementation of logic functions using only NAND (NOR) gates; Minimization of logic functions: Determining prime implicants using Karnaugh maps; Finding essential and sufficient prime implicants; Determining prime implicants using Tabular (Quine-McCluskey) method; Finding essential and sufficient prime implicants. MSI building blocks (Adders, multiplexers); Design of combinational logic circuits;Decoders, Programmable Logic devices (PAL, PLA); Latches and flip-flops; Analysis of synchronous sequential circuits; Design of synchronous sequential circuits; Electrical Behavior of logic circuits, TTL family; Characteristics of CMOS family
Course Outcomes		1) Working with signed and unsigned binary integer numbers 2) An ability to manipulate and simplify logic expressions using the postulates/theorems of Boolean algebra 3) An ability to generate the prime implicants of logic functions of 6 or fewer variables using graphical (Karnaugh map) and tabular (Quine-McCluskey) methods, and to obtain their implementations with and without don't cares. 4) An ability to implement simple digital systems using MSI building blocks (Adders, multiplexers, decoders). 5) An ability to understand the basic functional and timing (clocking) properties of state devices (latches and flip-flops). 6) An ability to analyze synchronous sequential circuits to extract their next-state/output functions and state tables. 7) An ability to translate a word statement specifying the desired behavior of a simple sequential system into a state table/diagram, and to design and implement the complete next-state and output logic from such tables.
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